1. Field of the Invention
The present invention relates to dynamic random access memory (DRAM) and structure and methods for accessing the same. More particularly, the present invention relates reducing the number of lines required to access DRAM.
2. Art Background
Dynamic random access memory (DRAM) components provide an inexpensive solid-state storage technology for today's computer systems. Digital information is maintained in the array in the form of a charge stored on a two-dimensional array of capacitors as is shown in FIGS. 1A and 1B. Accessing the array is a two step process. First, a row address is provided and held in a latch. This row address selects one of the rows of the DRAM by selecting a corresponding word line. The other word lines are deselected. If a read operation to the array is to be performed, a sense operation is performed in which the contents of the row of capacitors are detected through the selected row of transistors by the column amplifiers. If a write operation is to be performed, a restore operation is performed in which the contents of the column amplifiers are written to the row of capacitors of the array selected through the selected row of transistors. The sense operation is destructive requiring the row of capacitors to be subsequently recharged with a restore operation. As the column amplifiers are latching, the
FIG. 2 illustrates a prior art memory system including DRAM with the corresponding control, address and data wires which connect the DRAM to the processor or memory controller component. In one type of DRAM, an asynchronous (unclocked) interface is utilized in which the internal latches are loaded with the control signals. Today, synchronous DRAMs are typically used in which the interface contains internal latches and registers which employ an externally supplied clock source as the time reference. This permits the DRAM to transmit and receive information at a higher rate.
A write access is initiated by transmitting a row address on the address wires and by transmitting the sense control signal (RAS). This causes the desired row to be sensed by the column amplifiers at a time t.sub.RCD later. The column address is transmitted on the address wires and the write control signal (CAS) is transmitted along with the first word of the write data WData(a,1). The data word is then received by the DRAM and written into the column amplifiers at the specified column address. This step can be repeated "n" times in the currently sensed row before a new row is sensed. Before a new row is sensed, the old row must be restored back to the memory core and the bit lines of the DRAM precharged. Typically, there are two methods to achieve this in the DRAM. In a DRAM with a non-pulsed word line, every write operation causes the sensed row to be restored to the memory array. Thus, only a precharge is performed prior to the next sense operation. In a DRAM with a pulsed word line, the restore operation is done once just prior to the next precharge forward/sense operation.
FIG. 3 illustrates synchronous write timing when the size of the transmit/receive word, "tr" bits, equals the size of the read/write word, "rw" bits. In the figure, a, b . . . represents a row address; 1, 2 . . . n represent a column address,
FIG. 3 illustrates synchronous write timing when the size of the transmit/receive word, "tr" bits, equals the size of the read/write word, "rw" bits. In the figure, a, b . . . represents a row address; 1, 2 . . . n represent a column address, WData [row,col] represents the DRAM address of data word (rw bits) and sense (RAS) is a control signal for initiating a sense operation and WRITE(CAS) and READ(CAS) initiate the write and read operations, respectively, on the column amplifiers. In the present example, the row column address delay timing parameter t.sub.RCD is equal to two clock cycles. After the row address is asserted at the first clock cycle, column addresses and write data are asserted after the t.sub.RCD delay to write the data into the DRAM array.
A read access is initiated by the processor transmitting a row address on the address wires and by transmitting the sense control signal (RAS). This causes the desired row to be sensed by the column amplifiers. At a time t.sub.RCD later, the column address is transmitted on the address wires and the read control signal (CAS) is transmitted. At a time t.sub.CAA later, the first word of the read data RData (a,1) is transmitted by the DRAM and received by the processor. This step can be repeated "n" times in the currently sensed row before new row is sensed. Before a new row is sensed, the old row must be restored back to the memory array.
The read timing is illustrated by the timing diagram of FIG. 4. It should be noted that t.sub.CAA is the "column address access" timing parameter for the DRAM. This parameter specifies the delay between the issuance of the column address and the access to read data and represents the only real difference between read and write accesses.
It has been recognized that because of the length of time needed to perform a sense operation, it is not necessary for the row and column addresses types of synchronous DRAMs. Therefore, most DRAMs have approximately the same number of rows per array as column bits "sr" per row (wherein sr approximately equals b.sup.0.5, and b is the number of bits in the array). This maintains the number of row and column address signal lines to be roughly the same.
One trend in the DRAM technology is to increase the rate at which information is transmitted and received. This rate has been increasing in both absolute terms and in relative terms, when compared to the rate at which sense/restore operations and read/write accesses can be performed. FIG. 5 illustrates synchronous write timing, for f=2, when the time it takes to do a read or write access is half as slow as the time for data to be transmitted or received to the DRAM. Thus, in the time it takes to do a read or write access of "rw" bits, "f" words of "tr" bits each may be transmitted or received. In the figure, y, z, denote subfields which are tr bits in width of a data word rw bits in width. In addition, tcycle represents the time during which tr bits are transmitted/received at the DRAM input/output pins. The t.sub.read/write time parameter is the time to read/write rw bits to/from the column amplifiers, and t.sub.RCD is the time to sense a row and place it in the column amplifiers.